`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   14:32:06 11/07/2014
// Design Name:   InterfaceCircuit
// Module Name:   D:/Libraries/Documents/Ingenieria en computacion/Arquitectura Computadoras/Xilin/uart-arquitectura-2014/Test_fifo.v
// Project Name:  UART
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: InterfaceCircuit
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module Test_fifo;

	// Inputs
	reg clk;
	reg reset;
	reg rd;
	reg wr;
	reg [7:0] w_data;

	// Outputs
	wire full;
	wire empty;
	wire [7:0] r_data;
	

	// Instantiate the Unit Under Test (UUT)
	InterfaceCircuit #(.B(8), .W(2)) uut (
		.clk(clk), 
		.reset(reset), 
		.rd(rd), 
		.wr(wr), 
		.w_data(w_data), 
		.full(full), 
		.empty(empty), 
		.r_data(r_data),
		
	);

	initial begin
		// Initialize Inputs
		clk = 0;
		reset = 0;
		rd = 0;
		wr = 0;
		w_data = 0;

		// Wait 100 ns for global reset to finish
		#100;
		// Add stimulus here
		#50
		w_data = 8'b10101010;
		wr = 1;
		#200
		wr = 0;
		#200
		rd = 1;
		#200
		rd = 0;

	end
   
always begin
	#10
	clk = ~clk;
end
	
endmodule

